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MP8756 26v, 6a, low i q , high-current, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 1 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. the future of analog ic technology description the MP8756 is a fully integrated, high- frequency, synchronous, rectified, step-down, switch-mode converter. it offers a very compact solution that achieves 6a of continuous output current with excellent load and line regulation over a wide input supply range. the MP8756 operates with high efficiency over a wide output-current load range based on mps? proprietary switching loss reduction technique and internal low r ds(on) power mosfets. adaptive constant-on-time (cot) control mode provides fast transient response and eases loop stabilization. the dc auto-tune loop provides good load and line regulation. full protection features include over-current limit, over-voltage protection (ovp), under-voltage protection (uvp), and thermal shutdown. the converter requires a minimum number of external components and is available in a qfn- 12 (2mmx3mm) package. features ? wide 4.5v to 26v operating input range ? output adjustable from 0.6v ? ultrasonic mode (usm) ? 117 a low quiescent current ? 6a continous output current ? adaptive cot for fast transient ? dc auto-tune loop ? stable with poscap and ceramic output ? 1% reference voltage ? internal soft start ? output discharge ? 700khz switching frequency ? ocp, ovp, uvp (hiccup), and thermal shutdown ? available in a qfn-12 (2mmx3mm) package applications ? laptop computer ? tablet pc ? networking systems ? personal video recorders ? flat-panel television and monitors ? distributed power systems a ll mps parts are lead-free, halogen-free, and adhere to the rohs directive. fo r mps green status, please visit the mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc. typical application en vout bst vcc vin pg sw gnd v in gnd mode fb v out 1v/6a pgnd 22f 220nf 0.68h 88uf agnd 3.3 12v en 1f r4 499k c5 220pf r9 499 48.7k 66.5k MP8756 60.00 55.00 50.00 65.00 70.00 75.00 80.00 85.00 90.00 100.00 95.00 0.01 0.1 1 10
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 2 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. ordering information part number* package top marking MP8756gd qfn-12 (2mmx3mm) see below * for tape & reel, add suffix ?z (e.g. MP8756gd?z) top marking atq: product code of MP8756gd y: year code ww: week code lll: lot number package reference top view vcc agnd mode pgnd b s t sw vout vin 1 8 12 11 10 9 2 7 en pg nc fb 3 4 5 6 qfn-12 (2mmx3mm)
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 3 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. absolute maxi mum ratings (1) supply voltage (v in )...................................... 26v v sw ??????????? -0.6v to v in + 0.3v v sw (25ns)????????.. . -3v to v in + 4.5v v bst ??????????????. v sw + 4.5v v out ?????????????. -0.3v to 6.5v all other pins????????.. . -0.3v to +4.5v continuous power dissipation (t a =+25c) (2) qfn-12 (2mmx3mm)????????.. .. 1.8w junction temperature????????.. . 150c lead temperature?????????? .. 260c storage temperature................ -65 ? c to +150c recommended operating conditions (3) supply voltage (v in )??????.. . 4.5v to 24v output voltage (v out )??????. 0.6v to 5.5v operating junction temp. (t j )? -40c to +125c thermal resistance (4) ja jc qfn-12 (2mmx3mm)...............70 ...... 15 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation produces an excessive die temper ature, causing the regulato r to go into thermal shutdown. internal thermal shutdown circuitry protects the dev ice from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 4 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics v in = 12v, t a = 25c, unless otherwise noted. parameters symbol condition min typ max units supply current supply current (shutdown) i in v en = 0v 1 2 a supply current (quiescent) i in v en = 3.3v, v out = 5.5v 117 135 a mosfet high-side switch on resistance hs rds ( on ) 30 m ? low-side switch on resistance ls rds(on) 15 m ? switch leakage sw lkg v en = 0v, v sw = 0v 0 1 a current limit low-side valley current limit i limit 9 10.5 12 a switching frequency and timer switching frequency f s 700 khz constant on timer t on vin = 10v, vout = 5v, forced pwm mode 710 ns minimum on time ( 5 ) t on min 50 ns minimum off time ( 5 ) t off min 250 ns ultrasonic mode (usm) ultrasonic mode operation period t usm 20 30 40 s over-voltage (ovp) and under-voltage protection (uvp) ovp threshold v ovp rising 117% 122% 127% v ref ovp falling threshold v ovp falling 112% 117% 122% v ref uvp-1 threshold v uvp-1 70% 75% 80% v ref uvp-1 deglitch timer ( 5 ) t uvp-1 50 s uvp-2 threshold v uvp-2 45% 50% 55% v ref reference and soft start (ss) feedback voltage v ref 594 600 606 mv soft-start time t ss vout 10% to 90% 1.2 ms mode pwm mode input logic low threshold v mode_h 2.6 v pfm with usm threshold v mode mid 1.2 1.9 v pfm without usm threshold v mode l 0.4 v
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 5 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics (continued) v in = 12v, t a = 25c, unless otherwise noted. parameters symbol condition min typ max units enable and uvlo enable rising threshold v en h 1.15 1.25 1.35 v enable hysteresis v en-hys 100 mv enable input current i en v en = 2v 5 a v en = 0v 0 vin under-voltage lockout threshold rising vin vth 4 4.25 4.5 v vin under-voltage lockout threshold hysteresis vin hys 250 mv vcc regulator vcc regulator v cc 3.5 3.6 3.7 v vcc load regulation i cc = 5ma 5 % power good (pg) pg when fb rising (good) pg risin g( good ) v fb rising, percentage of v fb 95 % pg when fb falling (fault) pg fallin g( fault ) v fb falling, percentage of v fb 85 pg when fb rising (fault) pg risin g( fault ) v fb rising, percentage of v fb 115 pg when fb falling (good) pg fallin g( good ) v fb falling, percentage of v fb 105 power good low-to-high delay pg td 500 s en low to power good low delay pg td en low 1 s power good sink-current capability v pg sink 4ma 0.4 v power good leakage current i pg leak v pg = 3.3v 5 a thermal protection thermal shutdown ( 5 ) t sd 150 c thermal shutdown hysteresis ( 5 ) t sd-hys 25 c note: 5) guaranteed by engineering sample characterization.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 6 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 1v, l = 0.68h/3.1m ? , f s = 700khz, t a = +25c, pfm mode, unless otherwise noted. 0123456 70.00 75.00 80.00 85.00 90.00 95.00 100.00 0.01 0.1 1 10 70.00 75.00 80.00 85.00 90.00 95.00 100.00 0.01 0.1 1 10 70.00 75.00 80.00 85.00 90.00 95.00 100.00 0.01 0.1 1 10 60.00 55.00 50.00 65.00 70.00 75.00 80.00 85.00 90.00 100.00 95.00 60.00 55.00 50.00 65.00 70.00 75.00 80.00 85.00 90.00 100.00 95.00 60.00 55.00 50.00 65.00 70.00 75.00 80.00 85.00 90.00 95.00 0.01 0.1 1 10 0.01 0.1 1 10 0.01 0.1 1 10 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0123456 0123456 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.60
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 7 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1v, l = 0.68h/3.1m ? , f s = 700khz, t a = +25c, pfm mode, unless otherwise noted.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 8 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1v, l = 0.68h/3.1m ? , f s = 700khz, t a = +25c, pfm mode, unless otherwise noted.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 9 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1v, l = 0.68h/3.1m ? , f s = 700khz, t a = +25c, pfm mode, unless otherwise noted.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 10 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pin functions pin # name description 1 vin supply voltage. vin supplies power for the internal mosfet and regulator. the MP8756 operates from a 4.5v to 26v input rail. decoup le the input rail with an input capacitor. use wide pcb traces and multiple vias to make t he connection. apply at least two layers for this input trace. 2 pgnd power ground. connect using wide pcb traces and multiple vias large enough to handle the load current. 3 pg power good output. the output of pg is an open-drain signal. pg is high if the output voltage is higher than 95% or lower than 105% of the nominal voltage. 4 nc do not connect. nc must be left floating. 5 vout vout is used to sense the output voltage of the buck regulator. connect vout to the output capacitor of the regulator directly . keep the vout sensing trace far away from the sw node. vias should also be avoided on the vout sensing trace. a trace larger than 25mil is required. 6 mode usm, pfm, pwm selection. pull mode higher than 2.6v to operate the MP8756 in forced pwm mode. float mode to operate the MP8756 in pfm mode with ultrasonic mode (usm) at light load. connect mode to ground to operate the MP8756 in pfm mode without usm. 7 sw switch output. connect sw to the inductor and bootstrap capacitor. sw is driven up to vin by the high-side switch during the pw m duty cycle on-time. the inductor current drives sw negative during the off time. the on resistance of the low-side switch and the internal diode fixes the negative voltage. us e wide and short pcb traces to make the connection. keep the sw pattern area minimized. 8 bst bootstrap. a capacitor connected between sw and bst is required to form a floating supply across the high-side switch driver. 9 vcc internal vcc ldo output. the driver and control circuits are powered by vcc. decouple with a minimum 1f ceramic capacitor placed as close to vcc as possible. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. 10 agnd signal logic ground. agnd is the kelvin connection to pgnd. 11 fb feedback. fb sets the output voltage when connec ted to the tap of an external resistor divider connected between output and gnd. 12 en enable. en is a digital input that turns the r egulator on or off. when the power supply of the control circuit is ready, drive en high to tu rn on the regulator. drive en low to turn off the regulator.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 11 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. block diagram control logic on-time one shot fault logic soft start por & reference 122% vref ovp oc limit pok min off time vout 90% vref vout vin sw bstreg vin bst sw pgnd pg vcc output discharge v in v out dc error correction + + ref vref fb en agnd uvp-2 50% vref uvp-1 75% vref mode fb buf slope generator + + figure 1: functional block diagram
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 12 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. operation pwm operation the MP8756 is a fully integrated, synchronous, rectified, step-down, switch-mode converter. constant-on-time (cot) control is employed to provide a fast transient response and ease loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (v fb ) falls below the reference voltage (v ref ), which indicates an insufficient output voltage. the on period is determined by the output voltage and input voltage to make the switching frequency constant over the input voltage range. after the on period elapses, the hs-fet is turned off or enters an off state. it is turned on again when v fb drops below v ref . by repeating this operation, the converter regulates the output voltage. the integrated low-side mosfet (ls- fet) is turned on when the hs-fet is in its off state to minimize conduction loss. there is a dead short between the input and gnd if both the hs-fet and ls-fet are turned on at the same time. this is called a shoot-through. to avoid a shoot-through, a dead time (dt) is generated internally between hs-fet off and ls- fet on, or ls-fet off and hs-fet on. internal compensation is applied for cot control to make a more stable operation, even when ceramic capacitors are used as output capacitors. this internal compensation improves jitter performance without affecting line or load regulation. heavy-load operation continuous conduction mode (ccm) occurs when the output current is high and the inductor current is always above zero amps (see figure 2). when v fb is below v ref , the hs-fet is turned on for a fixed interval. when the hs-fet is turned off, the ls-fet is turned on until the next period. figure 2: heavy-load operation in ccm operation, the switching frequency is in pulse-width modulation (pwm) mode and is fairly constant. light-load power save mode the inductor current decreases as the load decreases. once the inductor current reaches zero, the operation switches from continuous conduction mode (ccm) to discontinuous conduction mode (dcm). the power save mode operation is shown in figure 3. when v fb is below v ref , the hs-fet is turned on for a fixed interval, which is determined by a one-shot on-timer, as shown in equation 1. when the hs-fet is turned off, the ls-fet is turned on until the inductor current reaches zero. in dcm operation, v fb cannot reach v ref while the inductor current is approaching zero. the ls- fet driver switches to tri-state (high-z) whenever the inductor current reaches zero. as a result, the efficiency at light load is greatly improved. in light-load condition, the hs-fet is not turned on as frequently as in heavy-load condition. this is called skip mode. at light-load or no-load condition, the output drops very slowly, and the MP8756 reduces the switching frequency to achieve high efficiency. figure 3: light-load operation as the output current increases from light-load condition, the current modulator regulation time period becomes shorter. the hs-fet is turned on more frequently, so the switching frequency increases correspondingly. the output current reaches critical levels when the current modulator time is zero. the critical level of the output current is determined with equation (1): in out out out sw in (v v ) v i 2lf v ?? ? ?? ? (1) the device enters pwm mode once the output current exceeds critical levels. afterward, the switching frequency remains fairly constant over the output current range.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 13 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. dc auto-tune loop the MP8756 applies a dc auto-tune loop to balance the dc error between v fb and v ref by adjusting the comparator input ref to make v fb follow v ref . this is a slow loop, so the load and line regulation improve without affecting the transient performance. the relationship between v fb , v ref , and ref is shown in figure 4. figure 4: dc auto-tune loop operation external ramp for low output voltage the MP8756 uses an internal ramp compensation control schem e to improve stability with a pure ceramic output capacitor. in some operating cases, the internal ramp amplitude is not sufficient to make the loop stable with ceramic capacitors. therefore, an extra external ramp around 20mv is needed for loop stabilization. please refer to the component selection section on page 15 for details. large duty operation the MP8756 can support larger duty operations with its internal t on extension function. when the part detects that fb is lower than v ref , and vin - vout < 2v, t on and the duty cycle can be extended. t on stops extending if fb is greater than ref or if t on meets its limitation. light-load ultrasonic mode (usm) ultrasonic mode (usm) is used to keep the switching frequency above audible frequency areas during light-load or no-load conditions. once the part detects that both the hs-fet and ls-fet are off for about 32s, t on shrinks to keep vout under regulation with optimal efficiency. if the load continues reducing, then the part discharges vout to ensure that fb is smaller than 102% of the internal reference. the hs-fet turns on again once the internal fb reaches v ref and then stops switching. usm is selected by the mode setting. float mode to operate the MP8756 in pfm mode with usm in light-load condition. configuring the en control to start up the MP8756 automatically, pull en up to the input voltage through a resistive voltage divider. please refer to the uvlo protection section on page 14 for details. mode selection mode is used to select the MP8756?s working mode. pull mode higher than 2.6v to operate the MP8756 in forced pwm mode. float mode to operate the MP8756 in pfm mode with usm at light load. connect mode to ground to operate the MP8756 in pfm mode without usm. soft start (ss) the MP8756 employs a soft-start (ss) mechanism to ensure a smooth output during power-up. when en rises high, the internal reference voltage and the output voltage ramp up gradually. once the reference voltage reaches its target value, the soft start finishes and the circuit enters steady-state operation. if the output is pre-biased to a certain voltage during start-up, the ic disables the switching of both the high-side and low-side switches until the voltage on the internal reference exceeds the sensed output voltage at the internal fb node. power good (pg) the MP8756 uses a power good (pg) output to indicate whether the output voltage of the buck regulator is ready or not. pg is the open drain of the mosfet and should be connected to vcc or another voltage source through a resistor (e.g.: 100k). after the input voltage is applied, the mosfet is turned on and pg is pulled to gnd before ss is ready. once the fb voltage reaches 95% of v ref , pg is pulled high after a 500s delay. when the fb voltage drops to 85% of v ref , pg is pulled low. when the output voltage is higher than 115% of the internal reference, pg is pulled low. pg rises high again after the output voltage drops below 105% of the internal reference voltage.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 14 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. over-current protection (ocp) the MP8756 has a cycle-by-cycle over-current limiting control. the current-limit circuit employs a valley current-sensing algorithm. the part uses the r ds(on) of the ls-fet as a current-sensing element. if the magnitude of the current-sense signal is above the current-limit threshold, pwm is not allowed to initiate a new cycle. the trip level is fixed internally. the inductor current is monitored by the voltage between gnd and sw. gnd is used as the positive current sensing node so that gnd should be connected to the source terminal of the bottom mosfet. since the comparison is done during the hs-fet off and ls-fet on states, the oc trip level sets the valley level of the inductor current. thus, the load current at the over-current threshold (i oc ) can be calculated with equation (2): ? ?? inductor oc i i i _ limit 2 (2) in an over-current condition, the current to the load exceeds the current to the output capacitor, and the output voltage can fall off. as a result, the device encounters the under-voltage protection threshold and hiccup. over-/under-voltage protection (ovp/uvp) the MP8756 monitors the output voltage to detect over-voltage and under-voltage. once the feedback voltage rises higher than 122% of the feedback voltage, the ovp comparator output goes high and the circuit turns off the hs-fet driver. the ls-fet driver turns on, acting as a current source. the output is then discharged to remain within the normal range. the MP8756 exits this regulation period when the feedback voltage falls below 117% of the reference voltage. when the feedback voltage falls below 75% of v ref but is higher than 50%, the uvp-1 comparator output goes high, and the part attempts to restart with hiccup mode periodically for about 50s if the feedback voltage remains in this range. when the feedback voltage falls below 50% of v ref , the uvp-2 comparator output goes high and the part enters hiccup mode directly after the comparator and logic delay. under-voltage lockout (uvlo) protection the MP8756 can start up only when vin is higher than the under-voltage lockout (uvlo) rising threshold voltage. the MP8756 shuts down when vin is lower than its falling threshold. the uvlo protection is non-latch off. if an application requires a higher uvlo, use en to adjust the input voltage uvlo by adding two external resistors (see figure 5). it is recommended to use the resistor divider to set the en voltage above the en rising threshold and below the 4.5v absolute maximum rating. the rising threshold should be set to provide enough hysteresis to allow for any input supply variations. to avoid an excessive sink current on en, keep the en resistor (r up ) in the range of 1m ? - 2m ? . a typical pull-up resistor is 1.5m ? . the r down value can then be determined by r up and a 600k ? internal pull-down resistor. figure 5: adjustable uvlo connecting en directly to a voltage source without a pull-up resistor requires limiting the amplitude of the voltage source. the en voltage must not exceed the 4.5v absolute maximum rating to avoid damaging the ic. thermal shutdown the MP8756 employs thermal shutdown. the junction temperature of the ic is monitored internally. if the junction temperature exceeds the threshold value (typically 140c), the converter shuts off. this is a non-latch protection. there is a hysteresis of about 25c. once the junction temperature drops to about 125c, a soft start is initiated. output discharge when en is low, the MP8756 discharges the output using an internal 6 ? mosfet.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 15 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. application information component selection setting the output voltage with an e- capacitor or pos capacitor for applications that use an electrolytic capacitor or pos capacitor with a controlled esr output is set as an output capacitor, external compensation is not need. the output voltage is set by feedback resistors r1 and r2 (see figure 6). r1 r2 esr poscap sw fb vo l figure 6: simplified circuit of pos capacitor the value for r2 must be chosen carefully since a small r2 value leads to considerable quiescent current loss, while a value that is too large makes fb noise sensitive. r2 is recommended to be within 5k ? - 100k ? . typically, set the current through r2 between 5a - 30a to create a good balance between the system stability and no-load loss. considering the output ripple, calculate r1 with equation (3): out ref ref vv r1 r2 v ? ?? (3) setting the output voltage with a pure ceramic output capacitor the MP8756 employs internal ramp compensation. when the internal compensation is enough for stable operation with the ceramic output capacitors, the external resistor divider is used to set v out . first, choose a value for r2. then r1 can be determined with equation (4): out ref ref vv r1 r2 v ? ?? (4) the feedback circuit is shown in figure 7. figure 7: feedback network when the internal ramp compensation is not enough to stabilize the loop with a pure ceramic capacitor, an extra external voltage ramp around 20mv should be added to fb through resistor r4 and capacitor c5. figure 8: external ramp compensation figure 8 shows a simplified external ramp compensation for pwm mode. v ramp on fb can be estimated with equation (5): ? ?? ? in out ramp on 45 vv vt rc (5) for better load or line regulation, use a lower v ramp . usually, v ramp is recommended to be around 20mv. the MP8756 employs a dc auto-tune loop to balance the dc error between v fb and v ref . v fb can maintain 0.6v, even with an external ramp compensation circuit. figure 9 shows the dc equivalent circuit with an external ramp circuit. figure 9: equivalent dc circuit
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 16 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. calculate r2 first, and then calculate r1 with equation (6): 1 fb 2outfb 4 9 1 r= v1 - r(v -v ) r+r (6) usually, r9 is set to 499 ? . it should be five times smaller than r1//r2 to minimize its influence on v ramp . r9 can also be set for better noise immunity with equation (7): 9 4sw 1 r 2c2f ? ?? ? (7) table 1 lists the recommended resistor values for common output voltages. table 1: resistor selection for common output voltages v out (v) r1 (k ? ) r2 (k ? ) l ( h) r4 (k ? ) c5 (pf) 1 48.7 66.5 0.68 499 220 1.2 52.3 47 0.95 499 220 1.5 82.5 47 0.95 499 220 1.8 115 47 0.95 499 220 2.5 43.2 12.7 1.2 499 330 3.3 43 9.63 1.5 ns ns 5 41.2 5.6 1.5 ns ns selecting the inductor the inductor is necessary for supplying a constant current to the output load while being driven by the switched input voltage. an inductor with a larger value results in less ripple current and a lower output ripple voltage. however, it also has a larger physical footprint, higher series resistance, and lower saturation current. a good rule for determining the inductance value is to design the peak-to-peak ripple current in the inductor to be in the range of 30% to 40% of the maximum output current to ensure that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated with equation (8): out out sw l in vv l(1) fi v ??? ?? (8) where ? i l is the peak-to-peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current. the peak inductor current can be calculated with equation (9): out out lp out sw in vv ii (1 ) 2f l v ?? ?? ? (9) selecting the input capacitor the input current to the step-down converter is discontinuous and therefore requires a capacitor to supply ac current to the step-down converter while maintaining the dc input voltage. use ceramic capacitors placed as close to vin as possible for best performance. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable with temperature fluctuations. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated with equation (10): out out cin out in in vv ii (1 ) vv ?? ?? (10) the worst-case condition occurs at v in = 2v out , shown in equation (11): out cin i i 2 ? (11) for simplification, choose an input capacitor with an rms current rating greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system, choose an input capacitor that meets the specification. the input voltage ripple can be estimated with equation (12): out out out in sw in in in iv v v(1) fc v v ?? ? ?? ? (12) under worst-case conditions where v in = 2v out , use equation (13): out in sw in i 1 v 4f c ??? ? (13)
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 17 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or pos capacitors are recommended. the output voltage ripple can be estimated with equation (14): out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc ?? ?? ? ? ??? (14) with ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated with equation (15): out out out 2 sw out in vv v(1) 8f lc v ?? ?? ??? (15) in the case of pos capacitors, the esr dominates the impedance at the switching frequency. the output ripple can be approximated with equation (16): out out out esr sw in vv v(1)r fl v ?? ?? ? ? (16) the maximum output capacitor limitation should be also considered during the design application. if the output capacitor value is too high, the output voltage cannot reach the design value during the soft-start time and fails to regulate. the maximum output capacitor value (c o_max ) can be limited approximately with equation (17): o_max lim_avg out ss out c(i i)t/v ??? (17) where i lim_avg is the average start-up current during a soft-start period, and t ss is the soft-start time. the inductance value can be calculated with equation (18): out out sw l in vv l(1) fi v ??? ?? (18) where ? i l is the peak-to-peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current, including short currents. i sat is recommended to be greater than 11.3a. pcb layout guidelines efficient pcb layout is critical for stable operation. a four-layer layout is strongly recommended to achieve a better thermal performance. for best results, refer to figure 10 and follow the guidelines below. 1. place the high current paths (gnd, in, and sw) very close to the device with short, direct, and wide traces. 2. place the input capacitors as close to in and gnd as possible. 3. place the decoupling capacitor as close to vcc and gnd as possible. 4. keep the switching node sw short and away from the feedback network. 5. keep the bst voltage path as short as possible with traces greater than 50mil. 6. keep the in and gnd pads connected with large copper traces to achieve better thermal performance. 7. add several vias with 10mil drill/18mil copper width close to the in and gnd pads to help with thermal dissipation.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 18 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. figure 10: recommend layout design example table 2 is a design example following the application guidelines for the specifications below: table 2: design example v in 12v v out 1v i out 6a the detailed application schematic for the 1v v out is shown in figure 17. the typical performance and waveforms are shown in the typical characteristics section. for more device applications, please refer to the related evaluation board datasheet.
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 19 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits pg vcc agnd pgnd bst figure 11: vin = 12v (6) , vo = 5v, io = 6a application schema tic with ceramic output capacitors pg vcc agnd pgnd bst figure 12: vin = 12v (6) , vo = 3.3v, io = 6a application sche matic with ceramic output capacitors figure 13: vin = 12v 6) , vo = 2.5v, io = 6a application sche matic with ceramic output capacitors
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 20 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits (continued) figure 14: vin = 12v (6) , vo = 1.8v, io = 6a application sche matic with ceramic output capacitors r5 1.5m c4 1f gnd l1 0.95h vin nc en mode fb sw vout r6 nc agnd r10 nc r7 nc r8 100k agnd vcc c6 100nf r3 3.3 c3 220nf r4 499k c5 220pf r9 499 r1 82.5k r2 47k c2a nc c2b 100nf c2c 22f c2d 22f c2e 22f c2f 22f c2g 100nf 1.5v vout gnd 100f optional c1a 22f c1b 22f c1c 100nf vin gnd gnd 1 4 12 6 3 9 10 2 11 5 7 8 vout figure 15: vin = 12v (6) , vo = 1.5v, io = 6a application sche matic with ceramic output capacitors r5 1.5m c4 1f gnd l1 0.95h vin nc en mode fb sw vout r6 nc agnd r10 nc r7 nc r8 100k agnd vcc c6 100nf r3 3.3 c3 220nf r4 499k c5 220pf r9 499 r1 52.3k r2 47k c2a nc c2b 100nf c2c 22f c2d 22f c2e 22f c2f 22f c2g 100nf 1.2v vout gnd 100f optional c1a 22f c1b 22f c1c 100nf vin gnd gnd 1 4 12 6 3 9 10 2 11 5 7 8 vout figure 16: vin = 12v (6) , vo = 1.2v, io = 6a application sche matic with ceramic output capacitors
MP8756 ? 26v, 6a, synchronous, step-down converter MP8756 rev. 1.1 www.monolithicpower.com 21 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits (continued) figure 17: vin = 12v (6) , vo = 1.0v, io = 6a application sche matic with ceramic output capacitors note: 6) the en resistor divider value should be modified accordingly with different input vo ltages. please refer to the uvlo protect ion section for details.
MP8756 ? 26v, 6a, synchronous, step-down converter notice: the information in this document is subject to change without notice. users should warrant and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP8756 rev. 1.1 www.monolithicpower.com 22 4/13/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package information qfn-12 (2mmx3mm) side view bottom view note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeters max. 4) jedec reference is mo-220. 5) drawing is not to scale. pin 1 id marking top view pin 1 id index area recommended land pattern

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